2003 · 13 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsMicroelectronicsCachingEmbedded Memory BlocksMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignCache ArchitectureCache DesignCache MemoryCache Memory DesignOn-chip Memory DesignStatic Random-access Memory Design
This 1.4 ns 700 MHz 4 kword/spl times/72 b embedded SRAM macro is intended for applications such as cache memory for system LSIs. The macro employs an easily expandable architecture. An 8 kword/spl times/72 b macro can be realized without loss of speed using two 4 kword/spl times/72 b macros.
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A 500 MHz 288 kb CMOS SRAM macro for on-chip cache
K. Furumochi, Haruo Shimizu, Masayuki Fujita et al. · 2002 · 12 citations