A novel asynchronous pipeline architecture for CISC type embedded controller, A8051

Abstract

Asynchronous design methods are known to have higher performance in power consumption and execution speed than synchronous ones because they just needs to activate the required module without feeding clock and power to the entire system. In this paper, we propose an asynchronous processor, A8051, compatible with the Intel 8051, which is a challenge for a pipelined asynchronous design for a CISC type microcontroller. The A8051 has special features such as an optimal instruction execution scheme that eliminates the bubble state, variable instruction length handling and multi-looping pipeline architectures for a CISC machine. The A8051 is composed of 5 pipeline stages based on the CISC architecture. It is implemented with RTL level languages and a verified behavioral model is synthesized with a 0.35 /spl mu/m CMOS standard cell library. The results show that the A8051 exhibits about 18 times higher speed than that of the Intel 80C51 and about 5 times higher than another asynchronous 8051 design in (H. van Gageldonk et al. Proc. Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, p.96-107, 1998).