2003 · 17 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsPower ManagementProcessor Core DesignProcessor MicroarchitectureBranch Target BuffersFloating-point InstructionsLocal Interconnect Network
The IBM G5 system is a fifth-generation CMOS server for the S/390 line of products with functionality improvements such as an instruction branch target buffer (BTB) and an IEEE compliant binary floating-point. The microprocessor operates at 600 MHz at the fast end of the process distribution, although the system is shipped at 500 MHz in a 10+2 SMP configuration. Measured system performance on the 10 way is 1069 S/390 MIPs. This microprocessor uses a 0.25 mum CMOS process. The chip uses 6 levels of metal plus an additional layer of local interconnect and is 14.6times14.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 25 M transistors (7 M logic/18 M array). Power supply is 1.9 V. Chip power is 25 W at 500 MHz
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IBM's S/390 G5 microprocessor design
T. J. Slegel, R. M. Averill, M. A. Check et al. · IEEE Micro · 1999 · 349 citations