Concepedia

A 90nm CMOS single-chip GPS receiver with 5dBm out-of-band IIP3 2.0dB NF

D. Sahu, Abhijit Das, Yogesh Darwhekar, Sudharsan Ganesan, R. Manoj Kumar, B.G. Chandrashekar, Amitava Ghosh, Ankit Gaurav, Abhilash Goyal, Shanthi Bhagavatheeswaran,

2005 · 35 citations · 2 references

DOI

Concepts

Abstract

A single-chip GPS receiver with a low-IF heterodyne RF front-end includes a LNA, image-reject IQ mixers, a passive poly-phase filter, and a fully integrated synthesizer. The IF-strip consists of a jammer-reject filter, a VGA, a /spl Delta//spl Sigma/ ADC, and a digital IF-filter. The receiver dissipates 60 mA at 1.4 V and achieves a NF of 2 dB and out-of-band IIP3 of 5 dBm.

References

2

A Complete Single-Chip GPS Receiver With 1.6-V 24-mW Radio in 0.18-<tex>$mu$</tex>m CMOS

T. Kadoyama, Norihito Suzuki, Noboru Sasho et al. · IEEE Journal of Solid-State Circuits · 2004 · 67 citations

, , +15

A fully-integrated GPS receiver front-end with 40 mW power consumption

Michiel Steyaert, Philippe Coppejans, Wouter De Cock et al. · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 34 citations

, , +15