Concepedia

Characterization and modeling of three CMOS diode structures in the CDM to HBM timeframe

Electrical Overstress/Electrostatic Discharge Symposium · 2006 · 40 citations · 9 references

Concepts

EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice CharacterizationDevice ModelingDevice SimulationDiode CircuitsIntegrated Circuit DesignArea EfficiencyDiode Circuit AnalysisMeasurement TechniquesTemperature Dependence Of Diodes

Abstract

We present advanced TLP measurement techniques down to 1.2ns pulses. We compare gated, STI and abutted tie diodes and introduce a compact model with a new thermal equivalent circuit fitting data in the entire CDM to HBM timeframe. Further, we compare diode area efficiency in a full ESD protection network.

References

9

Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies

Michael Stockinger, James W. Miller, Michael G. Khazhinsky et al. · 2003 · 93 citations

Engineering, Electrical Engineering, Circuit Theory +8

Latchup in CMOS technology

M. Hargrove, Steven H. Voldman, R. Gauthier et al. · 1998 · 61 citations

Engineering, Electrical Engineering, Microelectronics +13

Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

Cynthia A. Torres, James W. Miller, Michael Stockinger et al. · Microelectronics Reliability · 2002 · 56 citations

Engineering, Electrical Engineering, Circuit Theory +11

Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

Steven H. Voldman, James Nakos, John J. Pekarik et al. · 2002 · 52 citations

Engineering, Electrical Engineering, Microelectronics +10

VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing

Evan Grund, Robert Gauthier · 2004 · 31 citations

Engineering, Electrical Engineering, Systems Engineering +12