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Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope
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2013
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Electrical EngineeringEngineeringChannel Thin-film TransistorNanoelectronicsElectronic EngineeringApplied PhysicsGaa Poly-si NanosheetJunctionless TransistorsSemiconductor Device FabricationIdeal Subthreshold SlopeMicroelectronicsJl-gaa TftsJl TftsSilicon On InsulatorSemiconductor Device
A junctionless (JL) gate-all-around (GAA) nanosheet polycrystalline silicon (poly-Si) 2nm channel thin-film transistor (TFT) has been successfully demonstrated. The sub-threshold swing (SS) of 61 mV/decade has been the record reported to date in JL TFTs, and the Ion/Ioff current ratio is 108. The cumulative distribution in nanosheet 2-nm channel is small. JL-GAA TFTs show a low drain-induced barrier lowering (DIBL) value of 6 mV/V for LG=60nm, excellent gate control and reduced sensitivity to temperature in terms of VTH and SS. The JL-GAA TFTs of good device characteristics along with simple fabrication are highly promising for future (system-on-panel) SOP and system-on-chip (SOC) applications.