Design and analysis of a bus bar structure for a medium voltage inverter

Abstract

In order to suppress overvoltage of power devices and noise voltages of inverters, it is essential to analyze the DC-side inductance of the inverter. This paper presents a design procedure of an optimum structure for a 10-kV, 400-kVA three-level inverter. Rather than using 3D-FEM software, the bus bar inductance for the medium voltage inverter is calculated based on a partial inductance method. An inductance map is useful for determining the relationship between the bus bar structure and the inductance value and for designing the low-inductance structure. In addition, the calculation results of the bus bar inductance correspond to the measurement results, confirming the validity of the proposed method.