An 11-Bit 330MHz 8X OSR Σ-spl Delta/ Modulator for Next-Generation WLAN

Abstract

A 2-2 cascaded Sigma-Delta modulator with 4-bit internal quantizers digitizes WLAN signals with 40MSPS conversion rate. Implemented in 90nm CMOS using nominal-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> devices and metal comb capacitors, it occupies 1.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, achieves 67dB SNR, 63dB peak SNDR and 67dB peak SFDR at 330MHz, and dissipates 78mW from a 1.4V supply