A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors

Abstract

An emerging trend in microprocessor architecture for servers is to design chips with multiple processor cores on a chip called chip multi-processors (CMPs). Due to the short design cycle time and large size of these chips, the design-for-testability and testing of such chips is a major challenge. In this paper we describe a hierarchical DFT architecture for UltraSPARC/spl trade/ CMPs that is scalable with number of processor cores and can be implemented in a very short design cycle time. The DFT architecture allows testing of the processor cores individually for diagnosis as well as concurrently to reduce test application time and thus test cost. The DFT architecture can be easily ported across CMPs with different numbers of processor cores as well as to higher order CMPs designed by putting together CMPs.