2.5V Novel CMOS Circuit Techniques for a 150MHz Superscalar RISC Processor

Abstract

2.5V, novel CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 150MHz superscalar RISC processor. The processor makes use of a 0.3?m CMOS technology with a 2.5V power supply and 4 metal layers. The floating point macrocell has 380k transistors and dissipates 350mW at 150MHz. The peak performance of the floating point macrocell is 300MFLOPS.