Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L/sup 2/-GD) method

Abstract

As gate oxide thickness reduces, previous reported methods can not work well for very thin gate oxide devices as a result of the measured leakage current through the gate oxide. For the first time, a novel Low gate Leakage Gate-Diode (L/sup 2/-GD) method has been developed for the interface characterization of MOSFET devices with gate oxide in the direct tunneling regime. Three-peak experimental results, as seen from DCIV measurement, can be easily obtained from this L/sup 2/-GD method. This method has been demonstrated successfully for the ultra-thin (12-20 /spl Aring/) gate oxide device. Also, by using this new technique, the localized oxide damage due to NBTI or HC (Hot Carrier) stress effect can be identified simply from the measured drain currents. Therefore, this L/sup 2/-GD technique is well suited for the characterization of very thin gate oxide reliabilities, and in particular for the nano-scale CMOS devices.