Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC

Abstract

A consistent, fully hierarchical design methodology and design techniques developed to create the first single-chip full-duplex OC48 traffic manager and ATM SAR (segmentation and reassembly) IC are presented. The IC achieves a sustained throughput of 5 Gbps for 1 M simultaneous SAR flows. /spl sim/78 M transistors are integrated in a 0.15 /spl mu/m CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.