A double precision floating point multiply

Abstract

A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a 50% size reduction over the previously reported values. The circuit operates at 2.2GHz and uses 522mW at 80% switching factor, 1.2V supply and 25/spl deg/C.