A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS

Abstract

A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.