A CMOS to 100 K ECL interface circuit

Abstract

The authors have designed and fabricated a true CMOS/ECL (emitter-coupled logic) interface in a 0.9- mu m CMOS technology. This interface requires only a single external reference resistor to be completely ECL 100 K compatible. It accepts as input AC- or DC-coupled, differential or single-ended ECL 100 K signals and outputs the same. The interface demonstrates 100-MHz single-ended and 200-MHz differential operation while maintaining true ECL output levels and is part of a monolithic 200-MHz clock recovery circuit. Interface circuit characteristics are listed, and a block diagram is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>