High–speed architecture and hardware implementation of a 16–bit 100–MHz numerically controlled oscillator

Abstract

An architecture and hardware implementation of a numerically controlled oscillator is presented, based on a standard cell design in 0.7µ CMOS process. Sine/cosine, invoking a CORDIC-type algorithm, and triangle, saw-tooth and square-wave function generation are possible. Its key features are 16-bit signal amplitude output words at variable clock rates up to 100 MHz, a frequency resolution of 32 bit, and arbitrary real-time phase jumps at 16-bit resolution. The architecture was specifically tuned for speed performance employing mainly synchronised parallel processing topologies with a phased on-chip clock distribution. The pipe-line latency amounts to 24 clock cycles.