An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Abstract

Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AC</sub> ), due to significant summed input offsets (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OS-SUM</sub> ) at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AC</sub> of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a 1.53× improvement in TAC using AVB-CSA with a BL-length of 2048-rows operating at VDD=0.8 V.