Full Hold-Scan Systems in Microprocessors: Cost/Benefit Analysis

Abstract

Ever-shrinking microprocessor product development times require enhanced High-Volume Manufacturing (HVM) techniques. This paper describes the full holdscan testing system implemented in the 90nm Intel Pentium 4 processor. Benefits of this scan system include significantly reduced functional test-writing and fault-grade effort, extensive initialization of the design for test and debug, massive visibility into the design for postsilicon debug and fault isolation, and ultimately, a significantly accelerated ramp to production test quality. Any full hold-scan system such as this impacts timing, power, area, and schedule. In a high-performance microprocessor, in particular, this significantly impacts product viability and must be closely managed. In this paper, the Intel full hold-scan system is described, particularly the design challenges, cost optimizations, and test benefits, and we also discuss the costs and benefits of having implemented this successful testing system.