Concepedia

Wakeup Logic

Wakeup Logic is a hardware control mechanism in out-of-order execution processors that determines when an instruction's operands are ready by monitoring the availability of source operands across multiple reservation stations, thereby enabling the instruction to be issued to an execution unit.

35

Publications

2.6K

Citations

124

Authors

40

Institutions

Publications per year

2017–2026

5

Parents

Publications

35

Complexity-effective superscalar processors

Subbarao Palacharla, Norman P. Jouppi, James E. Smith · 1997 · 839 citations

, , +17

Somniloquy: augmenting network interfaces to reduce PC energy usage

Yuvraj Agarwal, Steve Hodges, Ranveer Chandra et al. · 2009 · 229 citations

, , +13

Radio-Triggered Wake-Up for Wireless Sensor Networks

Lin Gu, John A. Stankovic · Real-Time Systems · 2005 · 207 citations

, , +14

Complexity-effective superscalar processors

Subbarao Palacharla, Norman P. Jouppi, James E. Smith · ACM SIGARCH Computer Architecture News · 1997 · 133 citations · Full text

, , +17

On pipelining dynamic instruction scheduling logic

Jared Stark, Mary D. Brown, Yale N. Patt · 2000 · 132 citations

, , +17

1–5 of 35

Authors

124

  1. SP
    Subbarao Palacharla

    University of Wisconsin–Madison, United States

    3 publications · 1.1K citations

    3

    h-index

  2. JE
    James E. Smith

    University of Wisconsin–Madison, United States

    3 publications · 1.1K citations

    3

    h-index

  3. NP
    Norman P. Jouppi

    Hewlett-Packard (United States), United States

    3 publications · 1.1K citations

    3

    h-index

  4. OR
    Olivier Rochecouste

    Institut de Recherche en Informatique et Systèmes Aléatoires, France

    2 publications · 77 citations

    2

    h-index

  5. MD
    Mary D. Brown

    The University of Texas at Austin, United States

    2 publications · 153 citations

    2

    h-index

1–5 of 124

Institutions

40

  1. University of Wisconsin–Madison

    Madison, United States

    3 h-index

    7 publications

    3K citations

  2. The University of Texas at Austin

    Austin, United States

    3 h-index

    11 publications

    698 citations

  3. Intel (United States)

    Santa Clara, United States

    3 h-index

    5 publications

    195 citations

  4. University of Illinois Urbana-Champaign

    Urbana, United States

    2 h-index

    5 publications

    192 citations

  5. Massachusetts Institute of Technology

    Cambridge, United States

    2 h-index

    5 publications

    378 citations

  6. Centre Inria de l'Université de Rennes

    Rennes, France

    2 h-index

    6 publications

    231 citations

  7. Institut de Recherche en Informatique et Systèmes Aléatoires

    Rennes, France

    2 h-index

    6 publications

    231 citations

  8. Institut national de recherche en sciences et technologies du numérique

    Le Chesnay-Rocquencourt, France

    2 h-index

    6 publications

    231 citations

1–8 of 40

Venues

  1. IEEE Journal of Solid-State Circuits

    2 publications · 133 citations

    2

    h-index

  2. Real-Time Systems

    1 publications · 207 citations

    1

    h-index

  3. Minds at UW (University of Wisconsin)

    Repository · 1 publications · 125 citations

    1

    h-index

  4. ACM SIGARCH Computer Architecture News

    1 publications · 133 citations

    1

    h-index

  5. Ad Hoc Networks

    1 publications · 37 citations

    1

    h-index

1–5