Verification Specification

Verification Specification is a formal academic construct that belongs to the class of design specification artifacts, distinguished by its role in defining the criteria, methods, and processes used to evaluate whether a system or component conforms to its specified requirements.

38

Publications

1.3K

Citations

105

Authors

57

Institutions

Publications per year

2017–2026

4

Authors

105

  1. MD
    Michael D. Ernst

    University of Washington, United States

    4 publications · 253 citations

    4

    h-index

  2. RD
    Rolf Drechsler

    University of Bremen, Germany

    2 publications · 45 citations

    2

    h-index

  3. TW
    Todd W. Schiller

    University of Washington, United States

    2 publications · 33 citations

    2

    h-index

  4. MK
    Michael Kirsten

    Karlsruhe Institute of Technology, Germany

    1 publications · 10 citations

    1

    h-index

  5. FP
    F. Prunet

    Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, France

    1 publications · 22 citations

    1

    h-index

1–5 of 105

Venues

  1. Electronic Notes in Theoretical Computer Science

    ENTCS · 2 publications · 220 citations

    2

    h-index

  2. Computers in Industry

    1 publications · 22 citations

    1

    h-index

  3. ACM SIGPLAN Notices

    1 publications · 10 citations

    1

    h-index

  4. Kent Academic Repository (University of Kent)

    Repository · 1 publications · 31 citations

    1

    h-index

  5. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 1 publications · 27 citations

    1

    h-index

1–5