Verification Condition Generation

Verification Condition Generation is a deductive verification method that comprises the systematic derivation of logical formulas, whose validity entails correctness of a program with respect to a given specification.

42

Publications

2.9K

Citations

80

Authors

47

Institutions

Publications per year

2017–2026

4

Authors

80

  1. KR
    K. Rustan M. Leino

    Microsoft (United States), United States

    6 publications · 1.7K citations

    6

    h-index

  2. JB
    James B. Saxe

    Carnegie Mellon University, United States

    5 publications · 1.7K citations

    5

    h-index

  3. GN
    Greg Nelson

    Stanford University, United States

    4 publications · 1.6K citations

    4

    h-index

  4. ML
    Mark Lillibridge

    Hewlett-Packard (United States), United States

    4 publications · 1.6K citations

    4

    h-index

  5. RS
    Raymie Stata

    Microsoft (United States), United States

    4 publications · 1.6K citations

    4

    h-index

1–5 of 80

Venues

  1. ACM SIGPLAN Notices

    5 publications · 247 citations

    5

    h-index

  2. Proceedings of the ACM on Programming Languages

    PACMPL · 3 publications · 81 citations

    3

    h-index

  3. 2

    h-index

  4. Science of Computer Programming

    2 publications · 88 citations

    2

    h-index

  5. IEEE Transactions on Software Engineering

    TSE · 2 publications · 53 citations

    2

    h-index

1–5