Verification Condition Generation
Verification Condition Generation is a deductive verification method that comprises the systematic derivation of logical formulas, whose validity entails correctness of a program with respect to a given specification.
42
Publications
2.9K
Citations
80
Authors
47
Institutions
Publications per year
2017–2026
4
Parents
42
Extended static checking for Java
Cormac Flanagan, K. Rustan M. Leino, Mark Lillibridge et al. · 2002 · 1.3K citations
Inductive invariant generation via abductive inference
Thomas Dillig, Boyang Li, Ken McMillan · 2013 · 143 citations
Extended static checking for Java
Cormac Flanagan, K. Rustan M. Leino, Mark Lillibridge et al. · 2002 · 134 citations
Extended static checking for Java
Cormac Flanagan, K. Rustan M. Leino, Mark Lillibridge et al. · ACM SIGPLAN Notices · 2002 · 124 citations
Successive approximation of abstract transition relations
Satyaki Das, David L. Dill · 2002 · 112 citations
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47
Microsoft (United States)
Redmond, United States
9 h-index
14 publications
3.6K citations
Stanford University
Stanford, United States
5 h-index
6 publications
341 citations
Carnegie Mellon University
Pittsburgh, United States
3 h-index
5 publications
132 citations
University College London
London, United Kingdom
2 h-index
2 publications
186 citations
Institut national de recherche en sciences et technologies du numérique
Le Chesnay-Rocquencourt, France
2 h-index
3 publications
63 citations
KU Leuven
Leuven, Belgium
2 h-index
6 publications
228 citations
Williams (United States)
Tulsa, United States
2 h-index
2 publications
186 citations
Istituto di Analisi dei Sistemi ed Informatica Antonio Ruberti
Rome, Italy
2 h-index
5 publications
137 citations
1–8 of 47
5 publications · 247 citations
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PACMPL · 3 publications · 81 citations
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2 publications · 137 citations
2
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2 publications · 88 citations
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TSE · 2 publications · 53 citations
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