Trap-and-emulate Virtualization

Trap-And-Emulate Virtualization is a virtualization technique that belongs to the class of full virtualization methods, distinguished by its mechanism of intercepting privileged processor instructions through traps and subsequently emulating their intended behavior in the hypervisor to maintain the illusion of direct hardware access for guest operating systems.

5

Publications

755

Citations

6

Authors

4

Institutions

Publications per year

2017–2026

0

Authors

6

  1. OA
    Ole Agesen

    Kitware (United States), United States

    4 publications · 742 citations

    4

    h-index

  2. KA
    Keith Adams

    Kitware (United States), United States

    4 publications · 742 citations

    4

    h-index

  3. HG
    Haibing Guan

    Shanghai Jiao Tong University, China

    1 publications · 13 citations

    1

    h-index

  4. JL
    Jian Li

    Shanghai Jiao Tong University, China

    1 publications · 13 citations

    1

    h-index

  5. YD
    Yaozu Dong

    Shanghai Jiao Tong University, China

    1 publications · 13 citations

    1

    h-index

1–5 of 6

Institutions

4

Venues

  1. ACM SIGARCH Computer Architecture News

    1 publications · 28 citations

    1

    h-index

  2. ACM SIGPLAN Notices

    1 publications · 54 citations

    1

    h-index

  3. ACM SIGOPS Operating Systems Review

    1 publications · 42 citations

    1

    h-index

  4. 1

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1–4