Concepedia

Thread Block Scheduling

Thread Block Scheduling is a GPU execution management mechanism that assigns and coordinates the processing of thread blocks on streaming multiprocessors to optimize resource utilization and parallelism within a warp-based execution model.

40

Publications

1.2K

Citations

138

Authors

63

Institutions

Publications per year

2017–2026

18

Parents

Publications

40

Improving GPGPU resource utilization through alternative thread block scheduling

Minseok Lee, Seokwoo Song, Joosik Moon et al. · 2014 · 175 citations

, , +17

Massively LDPC Decoding on Multicore Architectures

Gabriel Falcão, Leonel Sousa, Vítor Silva · IEEE Transactions on Parallel and Distributed Systems · 2010 · 101 citations

, , +17

Warp-level divergence in GPUs: Characterization, impact, and mitigation

Ping Xiang, Yi Yang, Huiyang Zhou · 2014 · 77 citations

, , +17

Racing in Hyperspace: Closing Hyper-Threading Side Channels on SGX with Contrived Data Races

Guoxing Chen, Wenhao Wang, Tianyu Chen et al. · 2018 · 57 citations · Full text

, , +16

LaPerm

Jin Wang, Norm Rubin, Albert Sidelnik et al. · ACM SIGARCH Computer Architecture News · 2016 · 45 citations

, , +16

1–5 of 40

Authors

138

  1. HZ
    Huiyang Zhou

    North Carolina State University, United States

    3 publications · 132 citations

    3

    h-index

  2. LN
    Laxmi N. Bhuyan

    University of California, Riverside, United States

    3 publications · 81 citations

    3

    h-index

  3. JK
    John Kim

    Korea Advanced Institute of Science and Technology, South Korea

    2 publications · 190 citations

    2

    h-index

  4. JW
    Jin Wang

    Changsha University of Science and Technology, China

    2 publications · 77 citations

    2

    h-index

  5. ME
    Mehmet E. Belviranlı

    Oak Ridge National Laboratory, United States

    2 publications · 53 citations

    2

    h-index

1–5 of 138

Institutions

63

  1. University of Illinois Urbana-Champaign

    Urbana, United States

    5 h-index

    10 publications

    186 citations

  2. North Carolina State University

    Raleigh, United States

    4 h-index

    7 publications

    299 citations

  3. Nvidia (United States)

    Santa Clara, United States

    4 h-index

    4 publications

    95 citations

  4. Indian Institute of Science Bangalore

    Bengaluru, India

    3 h-index

    5 publications

    93 citations

  5. Sun Yat-sen University

    Guangzhou, China

    2 h-index

    2 publications

    31 citations

  6. Nvidia (United Kingdom)

    Reading, United Kingdom

    2 h-index

    4 publications

    154 citations

  7. Advanced Digital Sciences Center

    Singapore, Singapore

    2 h-index

    8 publications

    124 citations

  8. University of California, Irvine

    Irvine, United States

    2 h-index

    4 publications

    76 citations

1–8 of 63

Venues

  1. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 5 publications · 199 citations

    5

    h-index

  2. ACM Transactions on Architecture and Code Optimization

    TACO · 2 publications · 45 citations

    2

    h-index

  3. IEEE Computer Architecture Letters

    1 publications · 18 citations

    1

    h-index

  4. Performance Evaluation

    1 publications · 15 citations

    1

    h-index

  5. IEEE Transactions on Image Processing

    1 publications · 14 citations

    1

    h-index

1–5