Testbench Architecture
Testbench Architecture is a formal framework that specifies the structural and behavioral organization of a testbench, including the arrangement of components, stimulus generation, response monitoring, and evaluation mechanisms, to systematically validate the correctness and performance of a design under test within a targeted verification environment.
27
Publications
872
Citations
97
Authors
37
Institutions
Publications per year
2017–2026
5
Parents
27
Unit testing in multi-agent systems using mock agents and aspects
Roberta Coelho, Uirá Kulesza, Arndt von Staa et al. · 2006 · 93 citations
Beyond UVM for practical SoC verification
Young-Nam Yun, Jae‐Beom Kim, Namdo Kim et al. · 2011 · 61 citations
Ilya Loshchilov, Marc Schoenauer, Michèle Sébag · 2011 · 51 citations · Full text
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37

University of Victoria
Victoria, Canada
2 h-index
2 publications
91 citations

Amrita Vishwa Vidyapeetham
Coimbatore, India
2 h-index
4 publications
132 citations
Siemens (Germany)
Munich, Germany
2 h-index
2 publications
25 citations

The University of Queensland
Brisbane, Australia
2 h-index
2 publications
91 citations
Infineon Technologies (Germany)
Munich, Germany
2 h-index
9 publications
156 citations
Carnegie Mellon University
Pittsburgh, United States
1 h-index
2 publications
28 citations

University of Waterloo
Waterloo, Canada
1 h-index
1 publications
41 citations

Centre National de la Recherche Scientifique
Paris, France
1 h-index
1 publications
51 citations
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2 publications · 91 citations
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Conference · 1 publications · 22 citations
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1 publications · 23 citations
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Conference · 1 publications · 37 citations
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1 publications · 14 citations
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