Systemverilog Assertions
SystemVerilog Assertions is a formal verification construct within hardware description languages that enables the precise specification of design properties and temporal behaviors to be checked during simulation or formal analysis.
22
Publications
518
Citations
57
Authors
26
Institutions
Publications per year
2017–2026
8
Variants
Sva
Parents
22
(Security) Assertions by Large Language Models
Rahul Kande, Hammond Pearce, Benjamin Tan et al. · IEEE Transactions on Information Forensics and Security · 2024 · 70 citations · Full text
Synthesis of synchronous assertions with guarded atomic actions
Michael Pellauer, Muriel Bittencourt de Liz, D. Baltus et al. · 2005 · 32 citations
1–5 of 22
57
3
h-index
National University of Sciences and Technology, Pakistan
3 publications · 115 citations
3
h-index
3
h-index
3
h-index
2
h-index
1–5 of 57
26
National University of Sciences and Technology
Islamabad, Pakistan
3 h-index
6 publications
273 citations
University of California, Irvine
Irvine, United States
3 h-index
5 publications
128 citations
Umm al-Qura University
Makkah al Mukarramah, Saudi Arabia
3 h-index
4 publications
165 citations
New York University
New York, United States
2 h-index
6 publications
270 citations
Indian Institute of Technology Kharagpur
Kharagpur, India
2 h-index
6 publications
126 citations

University of Calgary
Calgary, Canada
2 h-index
2 publications
90 citations
Texas A&M University
College Station, United States
2 h-index
4 publications
180 citations

UNSW Sydney
Sydney, Australia
2 h-index
2 publications
90 citations
1–8 of 26
2 publications · 104 citations
2
h-index
Repository · 2 publications · 33 citations
2
h-index
1 publications · 70 citations
1
h-index
1 publications · 10 citations
1
h-index
TODAES · 1 publications · 28 citations
1
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1–5