Concepedia

Superscalar Control

Superscalar Control is a processor control design methodology that belongs to the class of instruction-level parallelism techniques, distinguished by its ability to issue and execute multiple instructions per clock cycle through dynamic scheduling and resource management across multiple execution units.

41

Publications

2K

Citations

150

Authors

48

Institutions

Publications per year

2017–2026

3

Parents

Publications

41

Limits of control flow on parallelism

Monica S. Lam, Robert P. Wilson · 1992 · 311 citations

, , +17

The microarchitecture of superscalar processors

James E. Smith, Gurindar S. Sohi · Proceedings of the IEEE · 1995 · 309 citations · Full text

, , +17

Limits of Control Flow on Parallelism

Monica S. Lam, Rory P. Wilson · 2005 · 126 citations

, , +17

Banked multiported register files for high-frequency superscalar microprocessors

Jessica H. Tseng, Krste Asanović · 2003 · 123 citations

, , +13

Techniques for verifying superscalar microprocessors

Jerry R. Burch · 1996 · 107 citations · Full text

, , +16

1–5 of 41

Authors

150

  1. JH
    Jessica H. Tseng

    IBM Research - Tokyo, Japan

    3 publications · 148 citations

    3

    h-index

  2. KA
    Krste Asanović

    University of California, Berkeley, United States

    3 publications · 148 citations

    3

    h-index

  3. MS
    Monica S. Lam

    Stanford University, United States

    3 publications · 486 citations

    3

    h-index

  4. JE
    James E. Smith

    University of Wisconsin–Madison, United States

    3 publications · 478 citations

    3

    h-index

  5. DJ
    D.B. Jackson

    PQ Corporation (Canada), Canada

    2 publications · 108 citations

    2

    h-index

1–5 of 150

Institutions

48

  1. University of Wisconsin–Madison

    Madison, United States

    3 h-index

    7 publications

    1K citations

  2. University of Toronto

    Toronto, Canada

    3 h-index

    7 publications

    149 citations

  3. IBM (United States)

    Armonk, United States

    3 h-index

    6 publications

    124 citations

  4. Stanford University

    Stanford, United States

    2 h-index

    3 publications

    409 citations

  5. Lawrence Berkeley National Laboratory

    Berkeley, United States

    2 h-index

    2 publications

    119 citations

  6. Cadence Design Systems (United States)

    San Jose, United States

    2 h-index

    2 publications

    119 citations

  7. Motorola (United States)

    Schaumburg, United States

    2 h-index

    7 publications

    166 citations

  8. Apple (United States)

    Cupertino, United States

    1 h-index

    1 publications

    26 citations

1–8 of 48

Venues

  1. ACM SIGARCH Computer Architecture News

    3 publications · 155 citations

    3

    h-index

  2. IEEE Micro

    2 publications · 44 citations

    2

    h-index

  3. Computer

    2 publications · 62 citations

    2

    h-index

  4. 33rd Design Automation Conference Proceedings, 1996

    Conference · 1 publications · 12 citations

    1

    h-index

  5. Journal of Electronic Testing

    JETTA · 1 publications · 13 citations

    1

    h-index

1–5