Speculative Store Execution is a processor optimization technique that belongs to the class of speculative execution methods, distinguished by its mechanism of executing store operations ahead of unresolved memory dependencies to improve instruction-level parallelism while ensuring architectural consistency through rollback upon misprediction.
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996
Citations
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Authors
17
Institutions
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2017–2026
0
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Publications
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S. Gopal, T. N. Vijaykumar, James E. Smith et al. · 2002 · 255 citations
Sentinel scheduling for VLIW and superscalar processors
Scott Mahlke, William Y. Chen, Wen‐mei Hwu et al. · 1992 · 120 citations · Full text
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Authors
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Institutions
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Purdue University West Lafayette
West Lafayette, United States
4 h-index
10 publications
806 citations
University of Pennsylvania
Philadelphia, United States
3 h-index
5 publications
333 citations
University of Wisconsin–Madison
Madison, United States
2 h-index
6 publications
1.1K citations
Network Technologies (United States)
Aurora, United States
1 h-index
1 publications
53 citations
Alcatel Lucent (Germany)
Stuttgart, Germany
1 h-index
1 publications
53 citations
Institute of Electrical and Electronics Engineers
Piscataway, United States
1 h-index
1 publications
65 citations
The Ohio State University
Columbus, United States
1 h-index
4 publications
60 citations
California University of Pennsylvania
California, United States
1 h-index
1 publications
62 citations
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- ACM SIGARCH Computer Architecture News
2 publications · 121 citations
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- IEEE Transactions on Parallel and Distributed Systems
TPDS · 2 publications · 118 citations
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- ACM SIGPLAN Notices
1 publications · 10 citations
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- ACM Transactions on Programming Languages and Systems
1 publications · 21 citations
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- International Symposium on Computer Architecture
Conference · 1 publications · 171 citations
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