Software Co-verification
Software Co-Verification is a verification methodology within embedded system design that integrates hardware and software models in a unified simulation environment to validate their functional correctness and dynamic interaction concurrently.
28
Publications
807
Citations
94
Authors
32
Institutions
Publications per year
2017–2026
8
Parents
28
Methodology for hardware/software co-verification in C/C++
Luc Séméria, Abhijit Ghosh · 2002 · 116 citations
ArchC: A SystemC-Based Architecture Description Language
Sandro Rigo, Guido Araújo, Marcus Bartholomeu et al. · 2004 · 98 citations
1–5 of 28
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32
University of Verona
Verona, Italy
3 h-index
10 publications
200 citations
University of Kaiserslautern
Kaiserslautern, Germany
2 h-index
5 publications
118 citations
National Cheng Kung University
Tainan City, Taiwan
2 h-index
5 publications
78 citations
Stanford University
Stanford, United States
2 h-index
2 publications
198 citations
Synopsys (United States)
Mountain View, United States
2 h-index
2 publications
198 citations
Seoul National University
Seoul, South Korea
2 h-index
9 publications
207 citations
Synopsys (Switzerland)
Zurich, Switzerland
2 h-index
2 publications
198 citations

Hanoi University of Science and Technology
Hanoi, Vietnam
1 h-index
1 publications
10 citations
1–8 of 32
TPDS · 1 publications · 19 citations
1
h-index
1 publications · 26 citations
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Conference · 1 publications · 11 citations
1
h-index
1 publications · 21 citations
1
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1 publications · 13 citations
1
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1–5