Software Co-verification

Software Co-Verification is a verification methodology within embedded system design that integrates hardware and software models in a unified simulation environment to validate their functional correctness and dynamic interaction concurrently.

28

Publications

807

Citations

94

Authors

32

Institutions

Publications per year

2017–2026

8

Authors

94

  1. FF
    Franco Fummi

    University of Verona, Italy

    3 publications · 58 citations

    3

    h-index

  2. PD
    Paolo Destro

    University of Verona, Italy

    2 publications · 32 citations

    2

    h-index

  3. WK
    Wolfgang Kunz

    University of Kaiserslautern, Germany

    2 publications · 37 citations

    2

    h-index

  4. AG
    Abhijit Ghosh

    Indian Institute of Technology Kharagpur, India

    2 publications · 198 citations

    2

    h-index

  5. LS
    Luc Séméria

    Stanford University, United States

    2 publications · 198 citations

    2

    h-index

1–5 of 94

Venues

  1. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 1 publications · 19 citations

    1

    h-index

  2. 1

    h-index

  3. 2020 IEEE International Systems Conference (SysCon)

    Conference · 1 publications · 11 citations

    1

    h-index

  4. Electronics

    1 publications · 21 citations

    1

    h-index

  5. IFAC-PapersOnLine

    1 publications · 13 citations

    1

    h-index

1–5