Single-Instruction Multiple-Thread Architectures is a parallel processing architecture in which a single instruction stream controls multiple threads of execution simultaneously, distinguishing it from other parallel models by synchronizing instruction-level concurrency across threads at the thread level rather than at the data level.
31
Publications
849
Citations
112
Authors
54
Institutions
Publications per year
2017–2026
8
Variants
Simt Architecture
Parents
Publications
31
Locality-Driven Dynamic GPU Cache Bypassing
Chao Li, Shuaiwen Leon Song, Hongwen Dai et al. · 2015 · 109 citations · Full text
The dual-path execution model for efficient GPU control flow
Minsoo Rhu, Mattan Erez · 2013 · 68 citations
1–5 of 31
Authors
112
- HZ
2
h-index
- YD
1
h-index
- HD
1
h-index
- JR
1
h-index
- PC
1
h-index
1–5 of 112
Institutions
54
North Carolina State University
Raleigh, United States
3 h-index
7 publications
401 citations
Pacific Northwest National Laboratory
Richland, United States
2 h-index
2 publications
120 citations
Advanced Micro Devices (Canada)
Markham, Canada
2 h-index
4 publications
106 citations
Nvidia (United States)
Santa Clara, United States
2 h-index
4 publications
262 citations
University of Perugia
Perugia, Italy
1 h-index
1 publications
45 citations
Freie Universität Berlin
Berlin, Germany
1 h-index
3 publications
147 citations
University of Washington
Seattle, United States
1 h-index
2 publications
28 citations
Chinese Academy of Sciences
Beijing, China
1 h-index
2 publications
26 citations
1–8 of 54
Venues
- Bioinformatics
2 publications · 63 citations
2
h-index
- IEEE Transactions on Information Forensics and Security
1 publications · 13 citations
1
h-index
- IEEE Transactions on Parallel and Distributed Systems
TPDS · 1 publications · 20 citations
1
h-index
- IEEE Transactions on Circuits and Systems for Video Technology
1 publications · 26 citations
1
h-index
- ACM SIGARCH Computer Architecture News
1 publications · 45 citations
1
h-index
1–5