Concepedia

Shared Memory Bank Conflicts

Shared Memory Bank Conflicts is a computational bottleneck in GPU architecture arising when multiple threads within a warp concurrently access different addresses that map to the same shared memory bank, thereby preventing simultaneous servicing of these accesses due to bank-level serialization.

23

Publications

1.2K

Citations

42

Authors

21

Institutions

Publications per year

2017–2026

4

Parents

Publications

23

A quantitative performance analysis model for GPU architectures

Yao Zhang, John D. Owens · 2011 · 272 citations · Full text

, , +17

Model-driven Level 3 BLAS Performance Optimization on Loongson 3A Processor

Qian Wang, Zhang Yunquan · 2012 · 184 citations

, , +17

Auto-tuning 3-D FFT library for CUDA GPUs

Akira Nukada, Satoshi Matsuoka · 2009 · 135 citations

, , +17

Fast scan algorithms on graphics processors

Yuri Dotsenko, Naga K. Govindaraju, Peter‐Pike Sloan et al. · 2008 · 129 citations

, , +17

A Novel Side-Channel Timing Attack on GPUs

Zhen Hang Jiang, Yunsi Fei, David Kaeli · 2017 · 66 citations

, , +15

1–5 of 23

Authors

42

  1. KN
    Koji Nakano

    Hiroshima University, Japan

    6 publications · 158 citations

    6

    h-index

  2. YI
    Yasuaki Ito

    Hiroshima University, Japan

    6 publications · 158 citations

    6

    h-index

  3. GG
    Georgi Gaydadjiev

    Delft University of Technology, Netherlands

    2 publications · 33 citations

    2

    h-index

  4. ZH
    Zhen Hang Jiang

    Northeastern University, United States

    2 publications · 89 citations

    2

    h-index

  5. CG
    Chunyang Gou

    Delft University of Technology, Netherlands

    2 publications · 33 citations

    2

    h-index

1–5 of 42

Institutions

21

  1. Hiroshima University

    Hiroshima, Japan

    6 h-index

    20 publications

    531 citations

  2. Northeastern University

    Boston, United States

    2 h-index

    5 publications

    244 citations

  3. Delft University of Technology

    Delft, The Netherlands

    2 h-index

    4 publications

    66 citations

  4. Japan Science and Technology Agency

    Tokyo, Japan

    1 h-index

    2 publications

    270 citations

  5. Tokyo Institute of Technology

    Tokyo, Japan

    1 h-index

    1 publications

    135 citations

  6. Microsoft (United States)

    Redmond, United States

    1 h-index

    5 publications

    645 citations

  7. Universidad de Málaga

    Málaga, Spain

    1 h-index

    2 publications

    80 citations

  8. Soongsil University

    Seoul, South Korea

    1 h-index

    1 publications

    11 citations

1–8 of 21

Venues

  1. 2

    h-index

  2. Computer Graphics Forum

    1 publications · 15 citations

    1

    h-index

  3. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 1 publications · 40 citations

    1

    h-index

  4. International Journal of Parallel Programming

    1 publications · 16 citations

    1

    h-index

  5. IEICE Transactions on Information and Systems

    1 publications · 11 citations

    1

    h-index

1–5