Shared Cache Design
Shared Cache Design is a multicore processor architecture strategy that employs a common cache memory accessible by all processor cores, distinguished from private cache designs by enabling direct data sharing and coherence across cores through a unified storage hierarchy.
131
Publications
6.5K
Citations
480
Authors
125
Institutions
Publications per year
2017–2026
21
131
Nikos Hardavellas, Michael Ferdman, Babak Falsafi et al. · 2009 · 382 citations · Full text
Adaptive insertion policies for managing shared caches
Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi et al. · 2008 · 300 citations
A NUCA substrate for flexible CMP cache sharing
Jaehyuk Huh, Changkyu Kim, Hazim Shafi et al. · 2005 · 221 citations
1–5 of 131
480
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3
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École Polytechnique Fédérale de Lausanne, Switzerland
3 publications · 442 citations
3
h-index
3
h-index
1–5 of 480
125
Intel (United States)
Santa Clara, United States
12 h-index
67 publications
3.8K citations

Pennsylvania State University
State College, United States
9 h-index
26 publications
1.3K citations
Stanford University
Stanford, United States
8 h-index
18 publications
791 citations
Advanced Micro Devices (United States)
Sunnyvale, United States
6 h-index
17 publications
476 citations
Carnegie Mellon University
Pittsburgh, United States
6 h-index
11 publications
1.7K citations
The University of Texas at Austin
Austin, United States
5 h-index
12 publications
1.5K citations
IBM Research - Austin
Austin, United States
4 h-index
14 publications
1.3K citations

University of Rochester
Rochester, United States
4 h-index
8 publications
155 citations
1–8 of 125
6 publications · 189 citations
6
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4 publications · 102 citations
4
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TPDS · 3 publications · 172 citations
3
h-index
3 publications · 153 citations
3
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Repository · 2 publications · 30 citations
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