Setup Delay

Setup Delay is a temporal constraint in digital circuit design that specifies the minimum amount of time an input signal must remain stable before the active edge of a clock signal to ensure reliable data capture, distinguishing it from hold delay by governing the earlier bound of signal stability relative to clocking events.

45

Publications

1.4K

Citations

133

Authors

56

Institutions

Publications per year

2017–2026

7

Authors

133

  1. RC
    Ramon Casellas

    Centre Tecnologic de Telecomunicacions de Catalunya, Spain

    3 publications · 59 citations

    3

    h-index

  2. RM
    Ricardo Martí­nez

    Centre Tecnologic de Telecomunicacions de Catalunya, Spain

    3 publications · 59 citations

    3

    h-index

  3. SA
    Samuli Aalto

    Aalto University, Finland

    2 publications · 32 citations

    2

    h-index

  4. VC
    Victor C. M. Leung

    University of British Columbia, Canada

    2 publications · 31 citations

    2

    h-index

  5. MV
    Malathi Veeraraghavan

    University of Virginia, United States

    2 publications · 29 citations

    2

    h-index

1–5 of 133

Venues

  1. 3

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  2. IEEE Communications Magazine

    3 publications · 76 citations

    3

    h-index

  3. Journal of Optical Communications and Networking

    JOCN · 3 publications · 135 citations

    3

    h-index

  4. 2

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  5. ACM SIGCOMM Computer Communication Review

    CCR · 1 publications · 24 citations

    1

    h-index

1–5