Setup Delay
Setup Delay is a temporal constraint in digital circuit design that specifies the minimum amount of time an input signal must remain stable before the active edge of a clock signal to ensure reliable data capture, distinguishing it from hold delay by governing the earlier bound of signal stability relative to clocking events.
45
Publications
1.4K
Citations
133
Authors
56
Institutions
Publications per year
2017–2026
7
Parents
45
1–5 of 45
133
Centre Tecnologic de Telecomunicacions de Catalunya, Spain
3 publications · 59 citations
3
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Centre Tecnologic de Telecomunicacions de Catalunya, Spain
3 publications · 59 citations
3
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2
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2
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2
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1–5 of 133
56
AT&T (United States)
Bedminster, United States
5 h-index
9 publications
275 citations

KTH Royal Institute of Technology
Stockholm, Sweden
4 h-index
12 publications
266 citations
Centre Tecnologic de Telecomunicacions de Catalunya
Barcelona, Spain
3 h-index
12 publications
208 citations
Kista Photonics Research Center
Kista, Sweden
2 h-index
8 publications
215 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
2 h-index
6 publications
138 citations
University of Science and Technology of China
Hefei, China
2 h-index
8 publications
500 citations
Aalto University
Espoo, Finland
2 h-index
5 publications
85 citations
Rutgers, The State University of New Jersey
New Brunswick, United States
2 h-index
2 publications
160 citations
1–8 of 56
3 publications · 41 citations
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3 publications · 76 citations
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JOCN · 3 publications · 135 citations
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2 publications · 173 citations
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CCR · 1 publications · 24 citations
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