Setup Analysis

Setup Analysis is a timing verification method used in digital integrated circuit design that determines whether a data signal arrives and remains stable at a capture flip-flop sufficiently before the clock edge to satisfy the setup time requirement, thereby ensuring correct state transfer within synchronous circuits.

39

Publications

1.4K

Citations

120

Authors

72

Institutions

Publications per year

2017–2026

5

Variants

Setup Time Analysis

Authors

120

  1. AD
    Alexandre Dolgui

    Centre National de la Recherche Scientifique, France

    2 publications · 27 citations

    2

    h-index

  2. AL
    An Liu

    City Of Hope National Medical Center, United States

    2 publications · 71 citations

    2

    h-index

  3. YC
    Yi‐Jen Chen

    City Of Hope National Medical Center, United States

    2 publications · 71 citations

    2

    h-index

  4. RD
    Richard D. Pezner

    City Of Hope National Medical Center, United States

    2 publications · 71 citations

    2

    h-index

  5. SK
    Sergey Kovalev

    Centre National de la Recherche Scientifique, France

    2 publications · 27 citations

    2

    h-index

1–5 of 120

Venues

  1. International Journal of Production Economics

    3 publications · 55 citations

    3

    h-index

  2. 2

    h-index

  3. Management Science

    2 publications · 41 citations

    2

    h-index

  4. Physics in Medicine and Biology

    2 publications · 105 citations

    2

    h-index

  5. 2

    h-index

1–5