Setup Analysis
Setup Analysis is a timing verification method used in digital integrated circuit design that determines whether a data signal arrives and remains stable at a capture flip-flop sufficiently before the clock edge to satisfy the setup time requirement, thereby ensuring correct state transfer within synchronous circuits.
39
Publications
1.4K
Citations
120
Authors
72
Institutions
Publications per year
2017–2026
5
Variants
Setup Time Analysis
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120
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72
Mines Saint-Étienne
Saint-Etienne, France
2 h-index
4 publications
53 citations

City Of Hope National Medical Center
Duarte, United States
2 h-index
15 publications
564 citations
Competence Centre on Health Technologies (Estonia)
Tartu, Estonia
1 h-index
1 publications
23 citations

University of Wisconsin–Milwaukee
Milwaukee, United States
1 h-index
1 publications
10 citations

University of Waterloo
Waterloo, Canada
1 h-index
4 publications
164 citations
Fudan University
Shanghai, China
1 h-index
1 publications
29 citations

Universidad de La Frontera
Temuco, Chile
1 h-index
4 publications
112 citations
Osaka International Cancer Institute
Osaka, Japan
1 h-index
2 publications
38 citations
1–8 of 72
3 publications · 55 citations
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2 publications · 71 citations
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2 publications · 41 citations
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2 publications · 105 citations
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2 publications · 104 citations
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1–5