Scheduling With Processor Failures

Scheduling with Processor Failures is a fault-tolerant scheduling model that specifically addresses the allocation of tasks in distributed computing systems where processor unavailability due to failures is explicitly incorporated into the scheduling constraints and execution timelines.

90

Publications

3.4K

Citations

216

Authors

135

Institutions

Publications per year

2017–2026

6

Authors

216

  1. MH
    Mourad Hakem

    Centre National de la Recherche Scientifique, France

    5 publications · 172 citations

    5

    h-index

  2. YR
    Yves Robert

    École Normale Supérieure de Lyon, France

    5 publications · 221 citations

    5

    h-index

  3. YS
    Yves Sorel

    Institut national de recherche en sciences et technologies du numérique, France

    4 publications · 135 citations

    4

    h-index

  4. AB
    Anne Benoît

    École Normale Supérieure de Lyon, France

    4 publications · 134 citations

    4

    h-index

  5. AG
    Alain Girault

    Institut national de recherche en sciences et technologies du numérique, France

    3 publications · 87 citations

    3

    h-index

1–5 of 216

Venues

  1. IEEE Transactions on Computers

    5 publications · 388 citations

    5

    h-index

  2. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 4 publications · 509 citations

    4

    h-index

  3. Theoretical Computer Science

    3 publications · 84 citations

    3

    h-index

  4. IEEE Transactions on Dependable and Secure Computing

    TDSC · 2 publications · 97 citations

    2

    h-index

  5. Computers & Industrial Engineering

    2 publications · 43 citations

    2

    h-index

1–5