Concepedia

Register Windows

Register Windows is a processor architectural method that employs overlapping sets of physical registers organized in a hierarchy of windows to optimize subroutine call and return operations by reducing the need for explicit memory accesses during parameter passing and local variable storage.

21

Publications

787

Citations

60

Authors

20

Institutions

Publications per year

2017–2026

0

Parents

Publications

21

MASA: a multithreaded processor architecture for parallel symbolic computing

Robert H. Halstead, Takeshi Fujita · ACM SIGARCH Computer Architecture News · 1988 · 142 citations

, , +17

Architecture of SOAR

David Ungar, Ricki Blau, Peter Foley et al. · ACM SIGARCH Computer Architecture News · 1984 · 98 citations · Full text

, , +16

Architecture of SOAR

David Ungar, Ricki Blau, Peter Foley et al. · 1984 · 82 citations · Full text

, , +16

Register windows vs. register allocation

David W. Wall · ACM SIGPLAN Notices · 2004 · 79 citations

, , +11

MASA: a multithreaded processor architecture for parallel symbolic computing

R.H. Halstead, T. Fujita · 2003 · 53 citations

, , +17

1–5 of 21

Authors

60

  1. HI
    H. Imori

    University of Tsukuba, Japan

    2 publications · 27 citations

    2

    h-index

  2. MR
    Matthew R. Guthaus

    University of California, Santa Cruz, United States

    2 publications · 42 citations

    2

    h-index

  3. RB
    Ricki Blau

    University of California, Berkeley, United States

    2 publications · 180 citations

    2

    h-index

  4. TL
    Tomás Lang

    University of California, Los Angeles, United States

    2 publications · 23 citations

    2

    h-index

  5. PF
    Peter Foley

    The University of Melbourne, Australia

    2 publications · 180 citations

    2

    h-index

1–5 of 60

Institutions

20

  1. University of Michigan

    Ann Arbor, United States

    3 h-index

    17 publications

    403 citations

  2. NEC (Japan)

    Tokyo, Japan

    2 h-index

    2 publications

    195 citations

  3. University of Tsukuba

    Tsukuba, Japan

    2 h-index

    6 publications

    81 citations

  4. University of California, Berkeley

    Berkeley, United States

    2 h-index

    10 publications

    900 citations

  5. Universitat Politècnica de Catalunya

    Barcelona, Spain

    1 h-index

    1 publications

    10 citations

  6. The University of Tokyo

    Tokyo, Japan

    1 h-index

    1 publications

    17 citations

  7. Stanford University

    Stanford, United States

    1 h-index

    1 publications

    47 citations

  8. Texas Instruments (United States)

    Dallas, United States

    1 h-index

    1 publications

    40 citations

1–8 of 20

Venues

  1. ACM SIGARCH Computer Architecture News

    3 publications · 253 citations

    3

    h-index

  2. ACM Transactions on Computer Systems

    TOCS · 1 publications · 10 citations

    1

    h-index

  3. 1

    h-index

  4. IEEE Journal of Solid-State Circuits

    1 publications · 20 citations

    1

    h-index

  5. IEEE Micro

    1 publications · 13 citations

    1

    h-index

1–5