Redundant Computing Architectures

Redundant Computing Architectures is a computing architecture that incorporates multiple active or standby processing components to ensure continued system operation in the presence of hardware or software failures, distinguishing itself from non-redundant architectures by its deliberate replication of computational resources for fault tolerance in safety-critical embedded systems.

28

Publications

1.9K

Citations

70

Authors

41

Institutions

Publications per year

2017–2026

3

Authors

70

  1. DD
    Debjit Das Sarma

    Southern Methodist University, United States

    1 publications · 40 citations

    1

    h-index

  2. SM
    S. Marrone

    University of Campania "Luigi Vanvitelli", Italy

    1 publications · 35 citations

    1

    h-index

  3. SC
    Siu-Cheung Chau

    Wilfrid Laurier University, Canada

    1 publications · 47 citations

    1

    h-index

  4. BD
    Björn Döbel

    Technische Universität Dresden, Germany

    1 publications · 51 citations

    1

    h-index

  5. GP
    Grzegorz Polaków

    Silesian University of Technology, Poland

    1 publications · 14 citations

    1

    h-index

1–5 of 70

Venues

  1. IEEE Transactions on Electronic Computers

    2 publications · 51 citations

    2

    h-index

  2. ACM Transactions on Embedded Computing Systems

    TECS · 1 publications · 13 citations

    1

    h-index

  3. Nanotechnology

    1 publications · 90 citations

    1

    h-index

  4. 1996 IEEE Aerospace Applications Conference. Proceedings

    Conference · 1 publications · 262 citations

    1

    h-index

  5. IEEE Transactions on Industry Applications

    1 publications · 19 citations

    1

    h-index

1–5