Processor Interconnection Topologies

Processor Interconnection Topologies is a structural framework that defines the specific arrangement and interconnection patterns of processing elements in a multiprocessor system, distinguishing it by determining the communication pathways, scalability, and performance characteristics relative to alternative configurations.

114

Publications

12K

Citations

300

Authors

121

Institutions

Publications per year

2017–2026

4

Variants

Processor Interconnect Topologies

Authors

300

  1. LN
    Laxmi N. Bhuyan

    University of California, Riverside, United States

    3 publications · 263 citations

    3

    h-index

  2. KP
    Krishnan Padmanabhan

    University of Rochester, United States

    3 publications · 244 citations

    3

    h-index

  3. SA
    S.G. Abraham

    University of Michigan, United States

    2 publications · 222 citations

    2

    h-index

  4. DP
    Dharma P. Agrawal

    University of Cincinnati, United States

    2 publications · 204 citations

    2

    h-index

  5. FI
    Finkel

    University of Wisconsin–Madison, United States

    2 publications · 72 citations

    2

    h-index

1–5 of 300

Venues

  1. IEEE Transactions on Computers

    13 publications · 1.2K citations

    13

    h-index

  2. Computer

    7 publications · 1.2K citations

    7

    h-index

  3. IEEE Micro

    6 publications · 1.5K citations

    6

    h-index

  4. Journal of Parallel and Distributed Computing

    5 publications · 295 citations

    5

    h-index

  5. ACM SIGARCH Computer Architecture News

    4 publications · 100 citations

    4

    h-index

1–5