Processor Front-End Bottlenecks is a processor performance limitation arising from the inability of the front-end stages—comprising instruction fetch, decode, and dispatch—to supply a sufficient stream of instructions to the execution units, thereby constraining the out-of-order execution engine’s ability to exploit instruction-level parallelism.
33
Publications
1.4K
Citations
97
Authors
39
Institutions
Publications per year
2017–2026
9
Parents
Publications
33
Supercomputing with commodity CPUs
Nikola Rajovic, Paul Carpenter, Isaac Gelado et al. · 2013 · 130 citations
Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling
Jike Chong, Nadathur Satish, Bryan Catanzaro et al. · 2007 · 82 citations
1–5 of 33
Authors
97
- RK
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- GR
4
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- BC
4
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- VN
3
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- BG
3
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1–5 of 97
Institutions
39
Intel (United States)
Santa Clara, United States
4 h-index
4 publications
193 citations
University of California San Diego
San Diego, United States
4 h-index
8 publications
416 citations
University of California, Berkeley
Berkeley, United States
3 h-index
11 publications
740 citations
Microcom (United States)
Lewis Center, United States
3 h-index
3 publications
162 citations
American Rock Mechanics Association
Alexandria, United States
3 h-index
9 publications
231 citations
University of Edinburgh
Edinburgh, United Kingdom
3 h-index
8 publications
346 citations
University of Michigan
Ann Arbor, United States
3 h-index
9 publications
250 citations
University of Rochester
Rochester, United States
2 h-index
4 publications
344 citations
1–8 of 39
Venues
- IEEE Computer Architecture Letters
2 publications · 43 citations
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- IEEE Transactions on Computers
2 publications · 59 citations
2
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- ACM SIGARCH Computer Architecture News
2 publications · 86 citations
2
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- Computing in Science & Engineering
1 publications · 71 citations
1
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- ACM SIGPLAN Notices
1 publications · 17 citations
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