Processor Bottleneck Analysis

Processor Bottleneck Analysis is a systematic methodological framework used in performance modeling and optimization that identifies and evaluates constraints within a computing system where processor capacity limits overall throughput, distinguishing itself by focusing specifically on quantifying processing-unit-induced limitations in relation to workload demands and system architecture.

38

Publications

1.7K

Citations

109

Authors

51

Institutions

Publications per year

2017–2026

2

Authors

109

  1. MS
    Muhammad Suleman

    The University of Texas at Austin, United States

    2 publications · 148 citations

    2

    h-index

  2. IB
    Iain Bate

    University of York, United Kingdom

    2 publications · 35 citations

    2

    h-index

  3. JA
    José A. Joao

    The University of Texas at Austin, United States

    2 publications · 148 citations

    2

    h-index

  4. UT
    Usman T. Khan

    York University, Canada

    2 publications · 35 citations

    2

    h-index

  5. YN
    Yale N. Patt

    The University of Texas at Austin, United States

    2 publications · 148 citations

    2

    h-index

1–5 of 109

Venues

  1. 2

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  2. American Scientist

    2 publications · 117 citations

    2

    h-index

  3. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 2 publications · 61 citations

    2

    h-index

  4. Ghent University Academic Bibliography (Ghent University)

    Repository · 1 publications · 32 citations

    1

    h-index

  5. Proceedings of the IEEE

    1 publications · 30 citations

    1

    h-index

1–5