Placement Aware Routing

Placement Aware Routing is a routing methodology in Network-on-Chip design that integrates physical placement information during route computation to optimize communication latency, power consumption, and resource utilization by minimizing the disparity between logical path selection and actual wirelength.

Publications

Citations

230

Authors

Institutions

Publications per year

2017–2026

Parents

Network-on-chip Design

Publications

A survey on application mapping strategies for Network-on-Chip design

Pradip Kumar Sahu, Santanu Chattopadhyay · Journal of Systems Architecture · 2012 · 337 citations

Engineering, Computer Engineering, Computer Science +14

A survey on physical layer impairments aware routing and wavelength assignment algorithms in optical networks

Siamak Azodolmolky, Mirosław Klinkowski, Eva Pérez Marín et al. · Computer Networks · 2008 · 283 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +16

A "Greedy" Channel Router

Ronald L. Rivest, Charles M. Fiduccia · 1982 · 278 citations

Engineering, Electrical Engineering, Channel Management +11

RouteNet

Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang et al. · 2018 · 208 citations

Computing, Computer Science, Computer Systems +17

Achieving predictable performance through better memory controller placement in many-core CMPs

Dennis Abts, Natalie Enright Jerger, John Kim et al. · 2009 · 149 citations

Engineering, Computer Engineering, Computer Science +16

1–5 of 87

Authors

230

CC
Chris Chu
Iowa State University, United States
4 publications · 348 citations
4
h-index
AE
Abbas El Gamal
Stanford University, United States
3 publications · 78 citations
3
h-index
RL
Ronald L. Rivest
Massachusetts Institute of Technology, United States
3 publications · 450 citations
3
h-index
CM
Charles M. Fiduccia
GE Global Research (United States), United States
3 publications · 450 citations
3
h-index
MM
Malgorzata Marek-Sadowska
University of California, Santa Barbara, United States
3 publications · 94 citations
3
h-index

1–5 of 230

Institutions

1–8 of 92

Venues

Design Automation Conference
Conference · 4 publications · 208 citations
4
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
4 publications · 193 citations
4
h-index
Journal of Network and Computer Applications
JNCA · 3 publications · 61 citations
3
h-index
EURASIP Journal on Embedded Systems
2 publications · 41 citations
2
h-index
Journal of Systems Architecture
JSA · 2 publications · 354 citations
2
h-index

1–5