Pipeline Verification

Pipeline Verification is a formal method for validating the correctness and consistency of computational stages and data flow in a pipeline parallelism system, distinguishing it from general verification techniques through its focus on inter-stage dependencies, synchronization, and stage-wise output integrity within the pipeline execution model.

35

Publications

1.3K

Citations

70

Authors

33

Institutions

Publications per year

2017–2026

4

Authors

70

  1. ND
    Nikil Dutt

    University of California, Irvine, United States

    6 publications · 117 citations

    6

    h-index

  2. PM
    Prabhat Mishra

    University of Florida, United States

    6 publications · 117 citations

    6

    h-index

  3. SK
    Sudarshan K. Srinivasan

    North Dakota State University, United States

    4 publications · 76 citations

    4

    h-index

  4. PM
    Panagiotis Manolios

    Georgia Institute of Technology, United States

    4 publications · 76 citations

    4

    h-index

  5. HT
    Hiroyuki Tomiyama

    Ritsumeikan University, Japan

    3 publications · 58 citations

    3

    h-index

1–5 of 70

Venues

  1. 33rd Design Automation Conference Proceedings, 1996

    Conference · 1 publications · 12 citations

    1

    h-index

  2. Mathematics and Computers in Simulation

    1 publications · 10 citations

    1

    h-index

  3. ACM Transactions on Embedded Computing Systems

    TECS · 1 publications · 30 citations

    1

    h-index

  4. Applied Mathematical Modelling

    1 publications · 26 citations

    1

    h-index

  5. Cognitive Psychology

    1 publications · 379 citations

    1

    h-index

1–5