Concepedia

Pipeline Depth Optimization

Pipeline Depth Optimization is a methodological framework in parallel computing that systematically determines the optimal number of pipeline stages to maximize throughput and minimize latency in deep learning model execution.

18

Publications

931

Citations

50

Authors

20

Institutions

Publications per year

2017–2026

2

Parents

Publications

18

Fast Elliptic Curve Cryptography on FPGA

William Chelton, Mohammed Benaissa · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2008 · 166 citations

, , +17

The optimum pipeline depth for a microprocessor

A. Hartstein, Thomas R. Puzak · ACM SIGARCH Computer Architecture News · 2002 · 148 citations

, , +17

Optimizing pipelines for power and performance

Viji Srinivasan, David Brooks, Michael Gschwind et al. · 2002 · 129 citations

, , +17

Optimizing pipelines for power and performance

V. Prasanna Srinivasan, David Brooks, Michael Gschwind et al. · 2003 · 79 citations

, , +17

Integrated analysis of power and performance for pipelined microprocessors

Victor Zyuban, David Brooks, V. Srinivasan et al. · IEEE Transactions on Computers · 2004 · 74 citations

, , +17

1–5 of 18

Authors

50

  1. AH
    A. Hartstein

    IBM Research - Thomas J. Watson Research Center, United States

    4 publications · 297 citations

    4

    h-index

  2. TR
    Thomas R. Puzak

    IBM Research - Thomas J. Watson Research Center, United States

    4 publications · 297 citations

    4

    h-index

  3. MG
    Michael Gschwind

    IBM Research - Thomas J. Watson Research Center, United States

    3 publications · 282 citations

    3

    h-index

  4. PE
    Philip Emma

    IBM Research - Thomas J. Watson Research Center, United States

    3 publications · 282 citations

    3

    h-index

  5. DB
    David Brooks

    Harvard University Press, United States

    3 publications · 282 citations

    3

    h-index

1–5 of 50

Institutions

20

  1. IBM Research - Thomas J. Watson Research Center

    Yorktown Heights, United States

    7 h-index

    28 publications

    2.4K citations

  2. Intel (United States)

    Santa Clara, United States

    2 h-index

    3 publications

    58 citations

  3. Motorola (United States)

    Schaumburg, United States

    2 h-index

    8 publications

    140 citations

  4. Qualcomm (United Kingdom)

    Farnborough, United Kingdom

    1 h-index

    5 publications

    65 citations

  5. TOBB University of Economics and Technology

    Ankara, Türkiye

    1 h-index

    1 publications

    24 citations

  6. Shibaura Institute of Technology

    Tokyo, Japan

    1 h-index

    1 publications

    20 citations

  7. Harvard University Press

    Cambridge, United States

    1 h-index

    1 publications

    74 citations

  8. Universitat Politècnica de Catalunya

    Barcelona, Spain

    1 h-index

    2 publications

    48 citations

1–8 of 20

Venues

  1. ACM Transactions on Architecture and Code Optimization

    TACO · 2 publications · 39 citations

    2

    h-index

  2. IEEE Transactions on Computers

    2 publications · 84 citations

    2

    h-index

  3. 1

    h-index

  4. ACM SIGARCH Computer Architecture News

    1 publications · 148 citations

    1

    h-index

  5. Circuits and Systems

    CS · 1 publications · 15 citations

    1

    h-index

1–5