Physical Clock Synchronization

Physical Clock Synchronization is a method for aligning the representations of time across distributed physical devices by minimizing the deviation between their hardware clock readings through direct time-stamp exchange and propagation delay estimation, distinguished from logical synchronization by its dependence on real-time measurement and hardware clock adjustments.

14

Publications

1.5K

Citations

29

Authors

14

Institutions

Publications per year

2017–2026

0

Authors

29

  1. MT
    Makoto Takizawa

    Rissho University, Japan

    2 publications · 34 citations

    2

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  2. KR
    Kay Römer

    Graz University of Technology, Austria

    2 publications · 737 citations

    2

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  3. AA
    Ailixier Aikebaier

    Rissho University, Japan

    2 publications · 34 citations

    2

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  4. TE
    Tomoya Enokido

    Rissho University, Japan

    2 publications · 34 citations

    2

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  5. NL
    Nancy Lynch

    Massachusetts Institute of Technology, United States

    2 publications · 443 citations

    2

    h-index

1–5 of 29

Venues

  1. 1

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  2. Journal of Communications and Networks

    1 publications · 13 citations

    1

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  3. Past & Present

    1 publications · 20 citations

    1

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  4. Information and Computation

    1 publications · 283 citations

    1

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  5. Journal of Simulation

    JOS · 1 publications · 14 citations

    1

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1–5