Phase-Locked Loop Modeling is a mixed-signal modeling framework that formally describes the dynamic behavior and synchronization mechanisms of phase-locked loops by integrating continuous-time analog components with discrete-time digital control elements within a unified computational structure.
371
Publications
17.8K
Citations
892
Authors
355
Institutions
Publications per year
2017–2026
95
Variants
Pll Modeling
Parents
Publications
371
Dong Dong, Bo Wen, Dushan Boroyevich et al. · IEEE Transactions on Industrial Electronics · 2014 · 701 citations
Engineering, Electrical Engineering, Systems Engineering +17
1–5 of 371
Authors
892
- JM
16
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- SG
13
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- RV
10
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- MV
10
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- JC
8
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1–5 of 892
Institutions
355
Aalborg University
Aalborg, Denmark
20 h-index
60 publications
5.5K citations
St Petersburg University
Saint Petersburg, Russia
10 h-index
27 publications
953 citations
University College Dublin
Dublin, Ireland
9 h-index
16 publications
281 citations
Politecnico di Milano
Milan, Italy
9 h-index
21 publications
554 citations
Southern Methodist University
Dallas, United States
8 h-index
10 publications
478 citations
Jet Propulsion Laboratory
Pasadena, United States
8 h-index
9 publications
763 citations
Centre National de la Recherche Scientifique
Paris, France
7 h-index
19 publications
665 citations
Universidade de São Paulo
São Paulo, Brazil
6 h-index
20 publications
481 citations
1–8 of 355
Venues
- IEEE Transactions on Power Electronics
26 publications · 2.4K citations
23
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- IRE Transactions on Communications Systems
25 publications · 1K citations
16
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- IEEE Transactions on Circuits and Systems I Regular Papers
17 publications · 631 citations
13
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- IEEE Transactions on Industrial Electronics
13 publications · 1.9K citations
13
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- IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
9 publications · 216 citations
9
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