Concepedia

Off-chip Memory Interface Design

Off-Chip Memory Interface Design is a hardware architecture methodology that specifies the electrical, timing, and protocol-level characteristics governing data exchange between a processor and external memory devices, distinguished from on-chip counterparts by its emphasis on signal integrity, package parasitics, and physical-layer optimization for high-speed, low-latency off-die communication.

20

Publications

507

Citations

76

Authors

25

Institutions

Publications per year

2017–2026

6

Parents

Publications

20

9.2 A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction

Huiyu Mo, Wenping Zhu, Wenjing Hu et al. · 2021 · 61 citations

, , +17

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014 · 45 citations

, , +17

A survey of FPGA design for AI era

Zhengjie Li, Yufan Zhang, Jian Wang et al. · Journal of Semiconductors · 2020 · 45 citations

, , +17

ShapeShifter

Alberto Delmás Lascorz, Sayeh Sharify, Isak Edo et al. · 2019 · 33 citations

, , +15

Flexible cache error protection using an ECC FIFO

Doe Hyun Yoon, Mattan Erez · 2009 · 28 citations

, , +17

1–5 of 20

Authors

76

  1. AB
    Andrew B. Kahng

    University of California San Diego, United States

    2 publications · 66 citations

    2

    h-index

  2. NP
    Norman P. Jouppi

    Hewlett-Packard (United States), United States

    2 publications · 66 citations

    2

    h-index

  3. OM
    Onur Mutlu

    Carnegie Mellon University, United States

    2 publications · 32 citations

    2

    h-index

  4. NM
    Naveen Muralimanohar

    Hewlett-Packard (United States), United States

    2 publications · 66 citations

    2

    h-index

  5. GA
    George A. Constantinides

    Imperial College London, United Kingdom

    2 publications · 37 citations

    2

    h-index

1–5 of 76

Institutions

25

  1. University of California San Diego

    San Diego, United States

    2 h-index

    4 publications

    132 citations

  2. Hewlett-Packard (United States)

    Palo Alto, United States

    2 h-index

    3 publications

    87 citations

  3. Imperial College London

    London, United Kingdom

    2 h-index

    5 publications

    84 citations

  4. University of Toronto

    Toronto, Canada

    2 h-index

    14 publications

    444 citations

  5. Shanghai Fudan Microelectronics (China)

    Shanghai, China

    1 h-index

    4 publications

    180 citations

  6. Washington University in St. Louis

    St Louis, United States

    1 h-index

    2 publications

    54 citations

  7. Tsinghua University

    Beijing, China

    1 h-index

    8 publications

    488 citations

  8. University of Michigan

    Ann Arbor, United States

    1 h-index

    6 publications

    162 citations

1–8 of 25

Venues

  1. arXiv (Cornell University)

    Repository · 2 publications · 32 citations

    2

    h-index

  2. Journal of Semiconductors

    1 publications · 45 citations

    1

    h-index

  3. 1

    h-index

  4. 1

    h-index

  5. 1

    h-index

1–5