Multistage Interconnection Networks

Multistage Interconnection Network is a class of switching architectures that interconnects processing elements and memory modules through multiple stages of switching elements, distinguished by its staged topology enabling scalable and efficient routing via intermediate switch stages rather than direct point-to-point or single-stage connections.

604

Publications

25.9K

Citations

1.1K

Authors

419

Institutions

Publications per year

2017–2026

36

Authors

1.1K

  1. FK
    F. K. Hwang

    AT&T (United States), United States

    12 publications · 379 citations

    11

    h-index

  2. YY
    Yuanyuan Yang

    Stony Brook University, United States

    11 publications · 588 citations

    11

    h-index

  3. PB
    Prateek Bansal

    National University of Singapore, Singapore

    10 publications · 219 citations

    10

    h-index

  4. HJ
    Howard Jay Siegel

    Colorado State University, United States

    10 publications · 457 citations

    10

    h-index

  5. LN
    Laxmi N. Bhuyan

    University of California, Riverside, United States

    10 publications · 353 citations

    10

    h-index

1–5 of 1.1K

Venues

  1. IEEE Transactions on Computers

    62 publications · 5.8K citations

    37

    h-index

  2. IEEE Transactions on Parallel and Distributed Systems

    TPDS · 30 publications · 989 citations

    17

    h-index

  3. IEEE Transactions on Communications

    21 publications · 855 citations

    16

    h-index

  4. Journal of Parallel and Distributed Computing

    18 publications · 938 citations

    13

    h-index

  5. IEEE Journal on Selected Areas in Communications

    13 publications · 422 citations

    12

    h-index

1–5