Multi-Level Cache Coherence is a cache coherence protocol that maintains data consistency across multiple hierarchical levels of caching in a shared-memory multiprocessor system, distinguishing itself by coordinating coherence actions across caches at different levels rather than within a single cache level.
6
Publications
363
Citations
9
Authors
5
Institutions
Publications per year
2017–2026
0
Parents
Publications
6
On the inclusion properties for multi-level cache hierarchies
J.-L. Baer, W.-H. Wang · 2003 · 91 citations
Maintaining I/O Data Coherence in Embedded Multicore Systems
Thomas B. Berg · IEEE Micro · 2009 · 22 citations
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Authors
9
- WW
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- LL
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- JB
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- DJ
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- WW
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1–5 of 9
Institutions
5
University of Washington
Seattle, United States
3 h-index
6 publications
626 citations
University of Illinois Urbana-Champaign
Urbana, United States
1 h-index
2 publications
30 citations
Seattle University
Seattle, United States
1 h-index
2 publications
98 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
1 h-index
1 publications
13 citations
IBM (United States)
Armonk, United States
1 h-index
1 publications
13 citations
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Venues
- IEEE Micro
1 publications · 22 citations
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- ACM SIGARCH Computer Architecture News
1 publications · 49 citations
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