Concepedia

Memory Traffic Reduction

Memory Traffic Reduction is a memory hierarchy optimization technique that minimizes data movement between memory levels by exploiting spatial and temporal locality, prefetching, or compression to decrease the volume of memory accesses required by a computing system.

202

Publications

9.8K

Citations

586

Authors

181

Institutions

Publications per year

2017–2026

40

Parents

Publications

202

Training Deep Nets with Sublinear Memory Cost

Tianqi Chen, Bing Xu, Chiyuan Zhang et al. · arXiv (Cornell University) · 2016 · 540 citations · Full text

, , +15

Using cache memory to reduce processor-memory traffic

James Goodman · 1998 · 396 citations

, , +17

Memory bandwidth limitations of future microprocessors

Doug Burger, James Goodman, Alain Kägi · 1996 · 394 citations · Full text

, , +17

HarDNet: A Low Memory Traffic Network

Ping Chao, Chao-Yang Kao, Yu-Shan Ruan et al. · 2019 · 328 citations

, , +13

Data Cache Prefetching Using a Global History Buffer

Kyle J. Nesbit, James E. Smith · 2005 · 307 citations

, , +14

1–5 of 202

Authors

586

  1. MV
    Mateo Valero

    Universitat Politècnica de Catalunya, Spain

    7 publications · 226 citations

    7

    h-index

  2. JG
    James Goodman

    University of Wisconsin–Madison, United States

    6 publications · 1.2K citations

    6

    h-index

  3. YL
    Youn-Long Lin

    National Tsing Hua University, Taiwan

    5 publications · 432 citations

    5

    h-index

  4. LB
    Luca Benini

    University of Bologna, Italy

    5 publications · 181 citations

    5

    h-index

  5. EM
    Enrico Macii

    Politecnico di Torino, Italy

    4 publications · 151 citations

    4

    h-index

1–5 of 586

Institutions

181

  1. University of Wisconsin–Madison

    Madison, United States

    12 h-index

    28 publications

    3.4K citations

  2. University of Michigan

    Ann Arbor, United States

    10 h-index

    15 publications

    1K citations

  3. University of Illinois Urbana-Champaign

    Urbana, United States

    8 h-index

    14 publications

    858 citations

  4. Intel (United States)

    Santa Clara, United States

    8 h-index

    11 publications

    535 citations

  5. Universitat Politècnica de Catalunya

    Barcelona, Spain

    8 h-index

    24 publications

    713 citations

  6. National Tsing Hua University

    Hsinchu, Taiwan

    6 h-index

    19 publications

    2K citations

  7. Seoul National University

    Seoul, South Korea

    5 h-index

    11 publications

    183 citations

  8. The University of Texas at Austin

    Austin, United States

    5 h-index

    8 publications

    659 citations

1–8 of 181

Venues

  1. ACM SIGARCH Computer Architecture News

    9 publications · 392 citations

    9

    h-index

  2. IEEE Transactions on Computers

    5 publications · 144 citations

    5

    h-index

  3. 5

    h-index

  4. 4

    h-index

  5. IEEE Transactions on Consumer Electronics

    3 publications · 42 citations

    3

    h-index

1–5