Memory Hierarchy Integration

Memory Hierarchy Integration is a framework in computer architecture that orchestrates the coherent and efficient interaction between processing accelerators and multiple levels of memory subsystems to optimize data locality, bandwidth utilization, and energy efficiency within heterogeneous computing environments.

91

Publications

6.4K

Citations

396

Authors

111

Institutions

Publications per year

2017–2026

21

Authors

396

  1. AN
    Andreas Nowatzyk

    Oracle (United States), United States

    3 publications · 262 citations

    3

    h-index

  2. JB
    Jean-Loup Baer

    University of Washington, United States

    2 publications · 40 citations

    2

    h-index

  3. HP
    H.‐S. Philip Wong

    Stanford University, United States

    2 publications · 240 citations

    2

    h-index

  4. MM
    Max M. Shulaker

    Stanford University, United States

    2 publications · 240 citations

    2

    h-index

  5. RD
    Ronald Dreslinski

    University of Michigan, United States

    2 publications · 98 citations

    2

    h-index

1–5 of 396

Venues

  1. IEEE Micro

    6 publications · 312 citations

    6

    h-index

  2. ACM SIGARCH Computer Architecture News

    3 publications · 412 citations

    3

    h-index

  3. ACM Transactions on Mathematical Software

    TOMS · 2 publications · 907 citations

    2

    h-index

  4. 2

    h-index

  5. Nature Electronics

    1 publications · 31 citations

    1

    h-index

1–5