Concepedia

Memory Coalescing

Memory Coalescing is a memory access optimization technique in GPU computing, wherein consecutive threads in a warp access adjacent memory locations, enabling the aggregation of multiple memory requests into fewer transactions by exploiting spatial locality and thereby increasing memory bandwidth utilization.

37

Publications

1.2K

Citations

130

Authors

64

Institutions

Publications per year

2017–2026

12

Parents

Publications

37

Assembly of finite element methods on graphics processors

Cris Cecka, Adrián J. Lew, Eric Darve · International Journal for Numerical Methods in Engineering · 2010 · 205 citations

, , +17

Supporting x86-64 address translation for 100s of GPU lanes

Jason Lowe-Power, David A. Wood · 2014 · 148 citations

, , +17

Memory access coalescing

Jack W. Davidson, Sanjay Jinturkar · 1994 · 89 citations

, , +13

Analyzing soft-error vulnerability on GPGPU microarchitecture

Jingweijia Tan, Nilanjan Goswami, Tao Li et al. · 2011 · 83 citations

, , +17

Network Motif Discovery: A GPU Approach

Wenqing Lin, Xiaokui Xiao, Xing Xie et al. · IEEE Transactions on Knowledge and Data Engineering · 2016 · 58 citations · Full text

, , +17

1–5 of 37

Authors

130

  1. AJ
    Adrián J. Lew

    Stanford University, United States

    2 publications · 215 citations

    2

    h-index

  2. SJ
    Sanjay Jinturkar

    University of Virginia, United States

    2 publications · 103 citations

    2

    h-index

  3. ED
    Eric Darve

    Stanford University, United States

    2 publications · 215 citations

    2

    h-index

  4. JW
    Jack W. Davidson

    University of Virginia, United States

    2 publications · 103 citations

    2

    h-index

  5. XX
    Xing Xie

    Microsoft Research Asia (China), China

    2 publications · 76 citations

    2

    h-index

1–5 of 130

Institutions

64

  1. University of Michigan

    Ann Arbor, United States

    2 h-index

    12 publications

    407 citations

  2. The Ohio State University

    Columbus, United States

    2 h-index

    4 publications

    116 citations

  3. École Normale Supérieure de Lyon

    Lyon, France

    2 h-index

    2 publications

    38 citations

  4. Agency for Science, Technology and Research

    Singapore, Singapore

    2 h-index

    4 publications

    152 citations

  5. Tsinghua University

    Beijing, China

    2 h-index

    5 publications

    62 citations

  6. Nanyang Technological University

    Singapore, Singapore

    2 h-index

    2 publications

    76 citations

  7. University of Virginia

    Charlottesville, United States

    2 h-index

    4 publications

    206 citations

  8. Microsoft Research Asia (China)

    Beijing, China

    2 h-index

    2 publications

    76 citations

1–8 of 64

Venues

  1. South African Computer Journal

    SACJ · 1 publications · 20 citations

    1

    h-index

  2. Tsinghua Science & Technology

    1 publications · 13 citations

    1

    h-index

  3. ACM SIGPLAN Notices

    1 publications · 14 citations

    1

    h-index

  4. ACM Transactions on Architecture and Code Optimization

    TACO · 1 publications · 12 citations

    1

    h-index

  5. The Journal of Supercomputing

    1 publications · 15 citations

    1

    h-index

1–5